3 GB barrier

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In computing, the term 3 GB barrier refers to a limitation of some 32-bit operating systems running on x86 microprocessors. It prevents the operating systems from using all of 4 GB (4 × 1024³ bytes) of main memory (RAM). The exact barrier varies by motherboard and I/O device configuration, particularly the size of video RAM; it may be in the range of 2.75 GB to 3.5 GB. The barrier is not present with a 64-bit processor and 64-bit operating system, or with certain x86 hardware and an operating system such as Linux or certain versions of Windows Server and macOS that fully support physical address extension (PAE) mode on x86.

Whatever the actual position of the "barrier", there is no code in operating system software nor any hardware architectural limit that directly imposes it. Rather, the "barrier" is the result of interactions between several aspects of both.

Video 3 GB barrier

Physical address limits

It is sometimes claimed that 32-bit processors and operating systems are limited to 4 GB (2³² bytes) of RAM, as were the original 80386DX and other early IA-32 CPUs. However, the Pentium Pro introduced the Physical Address Extension (PAE) mechanism, which allowed addressing up to 64 GB (2³⁶ bytes) of RAM; almost all subsequent 32-bit x86 processors also support PAE. PAE is a modification of the protected mode address translation scheme. It allows virtual or linear addresses to be translated to 36-bit physical addresses, instead of the 32-bit addresses available without PAE. The CPU pinouts likewise provide 36 bits of physical address lines to the motherboard.

Many x86 operating systems, including any version of Linux with a PAE kernel and some versions of Windows Server and Mac OS, support the use of PAE to address up to 64 GB of RAM on an x86 system.

Use of PAE to address RAM above the 4 GB point allows use of more than 3 GB. There are, however, factors that limit this ability, and lead to the "3 GB barrier" under certain circumstances, even though the processor fully supports PAE. These are described in the following sections.

Maps 3 GB barrier

Chipset and other motherboard issues

Although, as noted above, most x86 processors from the Pentium Pro onward do support physical addresses up to 64 GB, the rest of the motherboard must participate in allowing RAM above the 4GB point to be addressed by the CPU. Chipsets and motherboards allowing more than 4 GB of RAM with x86 processors do exist, but in the past, most of those intended for other than the high-end server market supported only 4 GB of RAM.

This, however, is not sufficient to explain the "3 GB barrier" that appears even when running some x86 versions of Microsoft Windows on platforms that do support more than 4 GB of RAM.

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Memory mapped I/O and disabled RAM

Modern personal computers are built around a set of standards that depend on, among other things, the characteristics of the original PCI bus. The original PCI bus supported 32-bit physical addresses and 32-bit wide data transfers. PCI (and PCI Express, and AGP) devices present at least some, if not all, of their host control interfaces via a set of memory-mapped I/O locations (MMIO). The address space in which these MMIO locations appear is the same address space as that used by RAM, and while RAM can exist and be addressable above the 4 GB point, these MMIO locations decoded by I/O devices cannot be. They are limited by PCI bus specifications to addresses of 0xFFFFFFFF (2³²-1) and below. With 4 GB or more of RAM installed, and with RAM occupying a contiguous range of addresses starting at 0, some of the MMIO locations will overlap with RAM addresses. On machines with large amounts of video memory, MMIO locations have been found to occupy as much as 1.8 GB of the 32-bit address space.

The BIOS and chipset are responsible for detecting these address conflicts and disabling access to the RAM at those locations. Due to the way bus address ranges are determined on the PCI bus, this disabling is often at a relatively large granularity, resulting in relatively large amounts of RAM being disabled.

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Address remapping

x86 chipsets that support more than 4 GB of RAM typically also support memory remapping (referred to in some BIOS setup screens as "memory hole remapping"). In this scheme, the BIOS detects the memory address conflict and in effect relocates the interfering RAM so that it may be addressed by the processor at a new physical address that does not conflict with MMIO. On the Intel side, this support once was limited to server chipsets; however, newer desktop chipsets like the Intel 955X and 965 and later support it as well. On the AMD side, the AMD K8 and later processors' built-in memory controller supported it from the beginning.

As the new physical addresses are above the 4 GB point, addressing this RAM does require that the operating system be able to use physical addresses larger than 2³². This capability is provided by PAE. Note that there is not necessarily a requirement for the operating system to support more than 4 GB total of RAM, as the total RAM might be only 4 GB; it is just that a portion of it appears to the CPU at addresses in the range from 4 GB and up.

This form of the 3 GB barrier affects one generation of MacBooks, lasting 1 year (Core2Duo (Merom) - Nov 2006 to Oct 2007): the prior generation was limited to 2 GB, while later generations (Nov 2007-Oct 2009) allowed 4 GB by supporting PAE and memory hole remapping, and subsequent generations (late 2009 onwards) use 64-bit processors and support over 4 GB.

src: ami.org

Windows version dependencies

In Microsoft's "non-server", or "client", x86 editions of Microsoft Windows (Windows XP, Windows Vista, Windows 7, Windows 8, Windows 8.1, and Windows 10), are able to operate x86 processors in PAE mode, and do so by default as long as the CPU present supports the NX bit. Nevertheless, these operating systems do not permit addressing of physical memory above the 4 GB address boundary. This is not an architectural limit; it is a limit imposed by Microsoft via license enforcement routines as a workaround for device driver compatibility issues that were discovered during testing.

Thus, the "3 GB barrier" under x86 Windows "client" operating systems can therefore arise in two slightly different scenarios. In both, RAM near the 4 GB point conflicts with memory-mapped I/O space. Either the BIOS simply disables the conflicting RAM; or, the BIOS remaps the conflicting RAM to physical addresses above the 4 GB point, but x86 Windows client editions refuse to use physical addresses higher than that, even though they are running with PAE enabled. The conflicting RAM is therefore unavailable to the operating system whether it is remapped or not.

src: science.sciencemag.org

See also

• 640 KB barrier
• x86-64
• PSE-36 -- an alternative to PAE on x86 processors to extend the physical memory addressing capabilities from 32 bits to 36 bits
• PCI hole
• Ring (computer security)
• RAM disk -- a use for remapped RAM
• Virtual memory -- which governs the memory available to processes
  • User space -- and kernel space, which imposes another limit

src: digitalconqurer.com

References

src: science.sciencemag.org

External links

• How to use full 4GB RAM in Windows 7 32 Bit (Gavotte RAMDisk in Windows 7)
• Why you should forget about 4GiB of RAM on 32-bit systems and move on

Source of article : Wikipedia